The process of extracting the timing pulse sequence is called bit synchronization [3], which is implemented by an external or a self-synchronization method.
The Principle of Bit Synchronization Clock Extraction Based on DPLL
When the descent edge of the bit synchronization signal is aligned with the edge detection signal, the input signal and the local synchronized clock signal are of the same frequency but reversed phase, making a synchronous illusion that the leading and lagging control pulses appear alternately in turns as shown in a real synchronization.
Zhang, "Design of bit synchronization circuit based on FPGA," Modern Electronics Technique, vol.
Lu, "Design of bit synchronization clock extraction circuit for wireless communication receiver," Electronic Technology, no.
When tracking loop is in bit synchronization tracking state, the sampling period is 1 millisecond.
The bit synchronization model starts working after the PLL has been locked by pulling frequency and phase for a typical receiver.
In above circumstances, in order to make the receiver still work well, we combine designed bit synchronization module with CDKF signal tracking module, so that a bit synchronization tracking is realized for very weak signals.
The bit synchronization in the red box refers to Section 2.
Simon, "Nonlinear analysis of an absolute value type of an early-late
bit synchronization," IEEE Transactions on Communications, vol.
Another advantage of this synchronous approach is that, in addition to
bit synchronization, word and cell synchronization can be performed between the transceivers and the switch chip.
The I and Q outputs of the SDC6400 go to conventional digital circuitry that performs decoding and
bit synchronization. Acquisition and tracking of the carrier is performed through digital feedback via a numerical-controlled oscillator that completes the quadrature subharmonically sampled Costas loop.