I am creating a design that must be portable across different tools: Xilinx Vivado, Intel Quartus, Microsemi Libero. The design uses multiplier followed by adder that accumulates the results from the multiplier. This forms a multiply-accumulate block.
I can include or exclude a register stage between the multiplier and the adder. My question is, how should it be decided if this should be included or excluded? Since the design could eventually be use in any tool for any FPGA, how do I decide what to do with that register stage?
The FSM design becomes a bit simpler without that register but the question is, how to reach a decision. Will not having a register there affect Fmax? Maybe. By how much it depends on the rest of the design on that FPGA. This is what causes the confusion.