“I worked with Shrutisagar for more than 4 years in Liquid Capital. He has relentless focus, tenacious work ethic and is a super smart innovative bold thinker with a result oriented mentality and one of the most impressive professionals I have ever had the pleasure to work with. I wouldn't hesitate for a nanosecond to recommend Shrutisagar.”
Activity
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I’m excited to announce a significant step forward in children's wellness at Sova Health: the launch of our new line of probiotics specially…
I’m excited to announce a significant step forward in children's wellness at Sova Health: the launch of our new line of probiotics specially…
Liked by Shrutisagar Chandrasekaran
Experience & Education
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Stripe
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Volunteer Experience
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Fundraiser
Eikon / Hope H.I.V.
- Present 15 years
Health
Publications
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Efficient Systolic Architecture and Power Modeling for Finite Ridglet Transform
5th IEEE workshop on embedded computer vision
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A New Behavioural Power Modelling Approach for FPGA based Custom Cores
Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)
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FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic
Signal Processing, IEEE Transactions on
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A segmentation concept for positron emission tomography imaging using multiresolution analysis
Elsevier Neurocomputing
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An Efficient VLSI Architecture and FPGA Implementation of the Finite Ridglet Transform
Journal of Real-Time Image Processing
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High Performance FPGA Implementation of the Mersenne Twister
4th IEEE International Symposium on Electronic Design, Test and Applications, 2008. DELTA 2008.
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FPGA Based Run Time Reconfigurable Gas Discrimination System
International Symposium on Integrated Circuits, 2007. ISIC '07.
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Performance Enhanced Voltage Scaling in FPGAs
IEEE International Symposium on Integrated Circuits, 2007. ISIC '07.
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A General Framework for Efficient FPGA Implementation and Power Modelling of Image Processing Cores
The IET visual information engineering conference 2007
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Novel Sparse OBC Based Distributed Arithmetic Architecture for Matrix Transforms
IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007.
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Power Modeling and Efficient FPGA Implementation of FHT for Signal Processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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An Efficient FPGA Implementation of Gaussian Mixture Models-Based Classifier Using Distributed Arithmetic
13th IEEE International Conference on Electronics, Circuits and Systems, 2006. ICECS '06.
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Power Modeling and Efficient FPGA Implementation of Color Space Conversion
13th IEEE International Conference on Electronics, Circuits and Systems, 2006. ICECS '06.
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FPGA Implementation and Power Modeling of FWT for Pattern Recognition
NASA Military and Aerospace Applications of Programmable Devices and Technologies Conference 2006
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Multi-Level Parallelism for Power and Energy Aware Design Verified Using Novel Functional Level Power Analysis & Modelling (FLPAM)
NASA Military and Aerospace Applications of Programmable Devices and Technologies Conference 2006
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FPGA Implementation and Power Modelling of the Fast Walsh Transform
International Conference on Field Programmable Logic and Applications, 2006. FPL '06.
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Power Reduction for FPGA Implementations: Design Optimisation and High Level Modelling
International Conference on Field Programmable Logic and Applications, 2006. FPL '06.
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An Area Efficient Low Power Inner Product Computation for Discrete Orthogonal Transforms
IEEE International Conference on Image Processing, 2005. ICIP 2005
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FPGA Implementation of Reduced Bit Plane Motion Estimation
NASA Military and Aerospace Applications of Programmable Devices and Technologies Conference 2005
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High Speed Energy Effcient Architectures for Finite Ridgelet Transform
NASA Military and Aerospace Applications of Programmable Devices and Technologies Conference 2005
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High Speed / Low Power Architectures for the Finite Radon Transform
IEEE International Conference on Field Programmable Logic and Applications, 2005
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An FPGA based Accelerator for the Finite Ridgelet Transform
IEEE International Computer Systems and Information Technology Conference 05
Other authors -
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A Novel Methodology for Temporal Partitioning in Self Reconfigurable Driven Multicontext FPGA
Postgraduate Research Conference in Electronics, Photonics, Communications and Networks, and Computing Science (PREP) 2005
Other authors -
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Automatic Damage Detection for Railroad Tracks by Real Time DSP Based Dual Analysis System
46th IEEE International Midwest Symposium on Circuits and Systems
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Double Abstraction Level Heuristic Power Optimization for Digital Signal Processors
46th IEEE International Midwest Symposium on Circuits & Systems
Languages
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English, Hindi, Tamil, Kannada
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